Information Age & Silicon Revolution (1960–1990)Microcomputers & Digital Hardware

Steve Wozniak's Apple II Personal Computer

US 4,136,359

Shared-Bus Time-Multiplexed Dynamic RAM & Digital NTSC Color Subcarrier Modulation

Inventor(s)Stephen G. Wozniak

Grant Date1979-01-23

Filing Date1977-04-11

LocationSan Jose, California

Wozniak's Apple II bus: video reads DRAM on 6502 Φ1, the CPU on Φ2, one set of chips, no wait states. Color on a stock TV comes from gating the 14.31818 MHz clock in 90° steps.

USPTO PDF

Engineering Analysis & Physical Principles

How It Works: Step-by-Step Mechanical & Physical Breakdown

Steve Wozniak designed the Apple II to be affordable, elegant, and blazingly fast. In 1977, video display cards cost hundreds of dollars and froze the CPU during raster refreshes. Wozniak's patent solved this with shared-bus memory multiplexing, making high-resolution color graphics standard on a home microcomputer.

The Core Breakthrough Mechanism

The MOS 6502 CPU only accesses memory during the high half of its clock cycle ( $Phi_2$ ). Wozniak gave the video display exclusive RAM access during the low half ( $Phi_1$ ). Both ran at full speed without wait states. Simultaneously, video raster scanning automatically refreshed the dynamic RAM rows and generated NTSC color via digital phase shifts.

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Detailed Component Architecture

1Two-Phase Shared Bus Multiplexer

74LS-series multiplexers switching address lines between CPU and Video.

During $Phi_1$ (489 ns), video counters read pixel bytes. During $Phi_2$ (489 ns), the 6502 CPU executes instructions. Memory contention is zero, and CPU throughput is 100%.

19th-C. Term: Multiplexing means for coupling video generator and microprocessorModern: Unified Memory Architecture (UMA) / Arbiter

2Digital NTSC Color Subcarrier Phase Modulator

Generating color on home TVs using 4 discrete digital phase taps.

Dividing the 14.31818 MHz master oscillator by 4 generates the 3.579545 MHz color reference. Gating pixel bits with 90-degree phase delays creates green, violet, blue, and orange colors.

19th-C. Term: Phase-shifting display pulses relative to color subcarrierModern: Digital Video Chroma Phase Synthesizer

3Automatic Dynamic RAM Row Refresh

Using video scan line counters to refresh 4116 DRAM capacitor cells.

Dynamic RAM requires reading every row address within 2 ms. The sequential vertical video scan automatically satisfies DRAM refresh cycles, eliminating complex refresh controller chips.

19th-C. Term: Dynamic random-access memory array refreshModern: DRAM auto-refresh controller

Governing Physical Equations & Principles

Time-Division Bus Multiplexing

T_{cycle} = t_{\Phi_1} + t_{\Phi_2} = 489\text{ ns} + 489\text{ ns} = 978\text{ ns} \implies f_{CPU} = 1.0227\text{ MHz}

Splitting the clock period gives both CPU and video full uninterrupted access to shared RAM every cycle.

NTSC Quadrature Color Phase Modulation

V_{color}(t) = Y(t) + I\cos(2\pi f_{sc} t) + Q\sin(2\pi f_{sc} t), \quad f_{sc} = 3.579545\text{ MHz}

Phase shifts relative to the 3.58 MHz color burst subcarrier modulate color hue and saturation on standard color TVs.

Why It Still Matters

Sharing one DRAM between a display and a CPU is still how a lot of small systems are built. Apple Silicon UMA is a distant cousin with a memory controller, not a 6502 clock phase, in the middle.

Legal Claims Decoder (2 Numbered Claims)

Compare dense legalistic claims directly with decoded plain-English functional specifications.

Claim #1Independent Master Claim

Verbatim Historical Legal Text

“1. In a microcomputer system including a microprocessor and a dynamic random-access memory array, a video display generation apparatus comprising: clock means for generating a two-phase clock signal having a first phase and a second phase; multiplexing means coupled to said microprocessor, said video display generator, and said dynamic random-access memory array for coupling said video display generator to said memory array during said first phase to retrieve display data therefrom, and for coupling said microprocessor to said memory array during said second phase to perform memory read and write operations; and video output means for converting the display data retrieved during said first phase into video signals for driving a display monitor.”

Plain English Engineering Translation

Covers the shared-bus multiplexing architecture that interleaves video display generation in Phase 1 and CPU program execution in Phase 2 across a single common RAM bank.

Key Protected Innovations:

Two-phase non-overlapping shared-bus memory multiplexingZero-wait-state CPU execution with transparent video display refreshUnified system and video RAM architecture

Historical Legal Impact:

The master patent claim for personal microcomputer shared memory display architectures.

The Historical Bottleneck

An Altair or IMSAI in 1976 was switches and a teletype. Video boards either used dual-port RAM nobody could afford or stole the CPU bus during the scan, so the machine stuttered whenever the beam was live.

Why Prior Art Failed

•DMA video: 30–50% of cycles gone.
•Dual-port frame buffers: cost more than the computer.
•Color on a TV usually meant a pile of analog parts.

The Breakthrough Insight

“The MOS 6502 only talks to the bus on Φ2. Φ1 is idle. Wozniak gave Φ1 to the video counters and Φ2 to the CPU. One set of cheap DRAM, no wait states, no flicker. The NTSC color trick (14.31818 MHz ÷ 4, gated phases) was the encore.”

Patent Wars & Legal Litigations

Vs. Commodore, Tandy, IBM (by architecture, not a single suit)Infringement Challenge

Rival Claim & Defense:

You can do home color without a shared-bus multiplexer.

Litigation Conflict:

PET and TRS-80 started as character-generator machines. IBM CGA (1981) used separate video RAM and 'snowed' when the CPU touched it during active scan. Apple II hi-res was already in living rooms.

Final Resolution & Judicial Outcome:

US 4,136,359 did not stop IBM. It did keep Apple's video design distinctive through the IIe era. VisiCalc shipped first on the II because the machine could update a screen without dying.

After the Grant

Jobs sold the company as appliances. Wozniak crashed a plane in 1981, came back briefly, and left day-to-day engineering. The IIgs was the last machine that still felt like his.

Civilizational Impact

Classrooms and small businesses bought a computer that showed color on the TV they already owned. That, more than the 1976 garage myth, is why the II matters.

Historical Fact

Wozniak wrote Integer BASIC and much of the early disk code by hand, hex on paper, then keyed it in. The Disk II controller is seven chips because he refused to use more.

Further Context

The 14.31818 MHz crystal is four times the NTSC color burst. That is not a coincidence.
Mike Markkola and the Homebrew club saw the prototype before there was a company. The patent is the bus; the culture is the club.