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Archaic Legal Glossary & Citations

“Letters Patent”14th–20th Century
19th-C Meaning:

Open public letters from a monarch or government (literae patentes) granting monopoly rights.

Modern Engineering Decoded:Issued USPTO utility or design patent publication.
Historical note: Contrasted with 'letters close' (private sealed royal correspondence).
“In testimony whereof”19th Century
19th-C Meaning:

Formal concluding legal formula affirming under oath the execution of the instrument.

Modern Engineering Decoded:Inventor and witness digital/physical signatures.
Historical note: Required two witness attestations in 19th-century USPTO filing procedure.
“Aeroplane”Early 20th Century (Wright era)
19th-C Meaning:

A flat or cambered lifting aerofoil surface supported dynamically by air pressure.

Modern Engineering Decoded:Wing / Airfoil lifting surface (later evolved to mean the entire motorized aircraft).
Historical note: The Wrights used 'aeroplane' to denote the individual fabric-covered wings.
“Undulating Current”19th Century (Bell era)
19th-C Meaning:

An electric current whose magnitude varies continuously and periodically without interruption.

Modern Engineering Decoded:Continuous analog AC or audio-frequency electrical waveform.
Historical note: Bell's central legal weapon against telegraph companies who relied on pulsed DC make-and-break circuits.
“Subdivision of the Electric Light”1870s–1880s (Edison era)
19th-C Meaning:

The problem of operating numerous small domestic lamps off a single electrical generator.

Modern Engineering Decoded:Parallel circuit wiring of high-resistance incandescent electrical loads.
Historical note: Pundits claimed it was physically impossible until Edison increased filament resistance to 100 ohms.
“Optically Anisotropic Solution”1960s (Kwolek era)
19th-C Meaning:

A liquid solution that exhibits direction-dependent refractive indices due to molecular alignment.

Modern Engineering Decoded:Liquid crystalline nematic phase polymer dope.
Historical note: Technicians initially tried to throw out Kwolek's cloudy solution thinking it was contaminated.
“Unitary Body of Semiconductor Material”1950s–1960s (Noyce era)
19th-C Meaning:

A single continuous crystal structure of silicon or germanium.

Modern Engineering Decoded:Monolithic single-crystal silicon die / integrated circuit wafer.
Historical note: Differentiated Noyce's monolithic planar circuit from Jack Kilby's hybrid flying-wire prototype.
“Peculiar and Novel Construction”19th Century
19th-C Meaning:

A distinctive, patentable structural arrangement not found in prior art.

Modern Engineering Decoded:Novel and non-obvious mechanical embodiment under 35 U.S.C. § 103.
Historical note: Standard 19th-century legal terminology establishing novelty.

Museum Broadside & Archival Print Edition

Authentic archival layout formatted for framing, study, and high-resolution printing

Paper:
Theme:
The United States Patent & Trademark Archive

Historical Specification & Engineering Broadside

Curated, Verified & Restored by Classic Patents (classic-patents.com)
MICROCOMPUTER FOR USE WITH VIDEO DISPLAYA crystal-locked horizontal timing correction and recirculating shift-register generator for color graphics on a raster television display.
US 4,136,359Class: H04N 9/44 (color television; color-signal generation)
Inventor(s):Stephen G. Wozniak
Origin / Location:Cupertino, California
Grant & Filing:Filed April 11, 1977 · Granted January 23, 1979

I. Historical Context & Grant Summary

US 4,136,359 describes a microcomputer video circuit that derives color directly from recirculating digital bits. Its timing circuit operates horizontal synchronization at an odd submultiple of the chroma reference, then inserts a controlled delay to keep successive raster lines aligned in color phase.

II. Core Mechanism & Scientific Principles

This grant addresses a television-timing problem that appeared when a home microcomputer tried to draw stable color graphics on an ordinary raster CRT. It uses one crystal reference for the video timing chain, deliberately compensates a line-to-line chroma phase reversal, and circulates digital color data through shift registers rather than generating and mixing separate analog color signals.

Physical Operation:The oscillator produces 14.31818 MHz, which the disclosed dividers reduce to the 7.15909 MHz and 3.579545 MHz timing relationships used by the circuit. The horizontal counter runs at about 15,734 Hz, an odd submultiple relationship that would otherwise shift chroma phase by 180 degrees each raster line. At a selected counter event, the shift-register counter waits two master-clock cycles, equal to half a chroma cycle, restoring vertical color alignment. Separately, RAM color bits circulate through two four-bit registers and a phase-select multiplexer to form a display-compatible output.
Governing Formulation:
Line-to-line chroma phase correction:Each 15,734 Hz line contains three and one-half 3.579545 MHz chroma cycles; a two-cycle delay at 14.31818 MHz supplies one-half chroma cycle.
Digital color generation by recirculation:Eight RAM bits load two four-bit registers at 1 MHz and are recirculated at 14.31818 MHz.

III. The Granted Legal Monopoly (Key Claims)

Claim 1 (Independent)color reference

Claims a video-display timing apparatus with three linked pieces: a color-reference source, horizontal synchronization that occurs at an odd submultiple of that reference, and a compensation circuit that adjusts horizontal timing so the signals remain phase-related. The claimed result is vertically sharp color graphics on a raster CRT.

Claim 2 (Dependent)digital horizontal counter

Narrows claim 1 by requiring the horizontal synchronization means to be a digital counter. It does not claim every counter in a video system; it keeps the parent timing and phase-compensation combination and specifies its horizontal-sync element.

Claim 3 (Dependent)periodic count delay

Further narrows the counter version by requiring the timing compensation to periodically delay counting. The legal work of this claim is the intermittent alteration of the counter sequence, not merely a continuously different clock rate.

IV. Mechanical Organ Breakdown

Crystal Reference and Divider ChainTerm: “timing reference means” → crystal-derived video clock and timing chain

Oscillator 51 and dividers 55 and 57 establish the master, half-rate, and color-subcarrier timing relationships shown in Figure 3.

Horizontal Counter CompensationTerm: “timing compensation means” → deterministic phase-correction interval

A temporary extension of the counter sequence adds half of a chroma cycle once per line to cancel the unwanted phase flip.

Recirculating Digital Color RegisterTerm: “recirculating shift register” → clocked digital serializer with feedback

Two four-bit shift registers accept color bits from RAM and repeatedly circulate them at the master-clock rate.

CLASSIC PATENTS DIGITAL ARCHIVE • PERMANENT EXHIBIT ID: us-4136359-wozniak-apple
classic-patents.com/patents/us-4136359-wozniak-apple
Original USPTO PDF
Classic Patents/US 4,136,359
Information Age & Silicon Revolution (1960–1990)Microcomputers & Digital Hardware

Wozniak Video Timing and Color Circuit

US 4,136,359

A crystal-locked horizontal timing correction and recirculating shift-register generator for color graphics on a raster television display.

Inventor(s)Stephen G. Wozniak
Grant DateJanuary 23, 1979
Filing DateApril 11, 1977
LocationCupertino, California
US 4,136,359 describes a microcomputer video circuit that derives color directly from recirculating digital bits. Its timing circuit operates horizontal synchronization at an odd submultiple of the chroma reference, then inserts a controlled delay to keep successive raster lines aligned in color phase.
USPTO PDF
Audio Engineering Breakdown~1 min listen

Listen to the narrated mechanical breakdown and civilizational context

Engineering Analysis & Physical Principles

How It Works: Step-by-Step Mechanical & Physical Breakdown

This grant addresses a television-timing problem that appeared when a home microcomputer tried to draw stable color graphics on an ordinary raster CRT. It uses one crystal reference for the video timing chain, deliberately compensates a line-to-line chroma phase reversal, and circulates digital color data through shift registers rather than generating and mixing separate analog color signals.
The Core Breakthrough Mechanism

The oscillator produces 14.31818 MHz, which the disclosed dividers reduce to the 7.15909 MHz and 3.579545 MHz timing relationships used by the circuit. The horizontal counter runs at about 15,734 Hz, an odd submultiple relationship that would otherwise shift chroma phase by 180 degrees each raster line. At a selected counter event, the shift-register counter waits two master-clock cycles, equal to half a chroma cycle, restoring vertical color alignment. Separately, RAM color bits circulate through two four-bit registers and a phase-select multiplexer to form a display-compatible output.

Interactive Real-Time Physical Simulation

Drag to rotate · Pinch to zoom · Shared controls update the displayed model
INITIALIZING THREE.JS WEBGL SIMULATION...
Two-Phase Non-Conflicting DRAM Bus Arbitration & Video Sync.
Host-Model Telemetry/Computed Readout
Two-Phase Non-Conflicting DRAM Bus Arbitration & Video Sync
Microprocessor Clock
1.023MHz[1/T]
NTSC Color Burst
3.579MHz[1/T]
DRAM Access Window
488.8ns[T]
Bus Contention Wait
0cycles[1]
Demo Tick
147 msΔt[1]
Visual Φ2
4Hz[1/T]
Φ2 CPU Duty
100%duty[1]
Video Dot Clock Bandwidth
∂BW / ∂f_osc (host sensitivity)
1 MHz / MHz
Master Quartz Crystal14.318 MHz
RAM Capacity48 KB
Energy · semiconductor_carrier
DC Power Supply
15 W
6502 CPU & DRAM Logic
12 W
Regulator Heat Dissipation
4 W
Interval ghosts
Φ2488.8 ns · [200, 800]
Fidelity / MMS residual
DRAM refresh cycle window vs 1976 Homebrew demo
model488 ns
reference488 ns
residual0 ns
Coupled channels
DC supply → 6502 CPU logic12 W
Dated scenarios

Detailed Component Architecture

1Crystal Reference and Divider Chain
Oscillator 51 and dividers 55 and 57 establish the master, half-rate, and color-subcarrier timing relationships shown in Figure 3.

The source gives 14.31818 MHz on line 33, 7.15909 MHz on line 56, and 3.579545 MHz on line 58. Those signals keep the color reference and the horizontal-timing correction tied to a common clock rather than to independent oscillators.

19th-C. Term: timing reference meansModern: crystal-derived video clock and timing chain
2Horizontal Counter Compensation
A temporary extension of the counter sequence adds half of a chroma cycle once per line to cancel the unwanted phase flip.

Counter 63 runs at approximately 15,734 Hz. Because its line period contains three and a half chroma cycles, the source says a two-cycle delay at 14.318 MHz is inserted when the prescribed count occurs. Two master-clock cycles equal 180 degrees at 3.58 MHz, so the color relationship is restored line-to-line.

19th-C. Term: timing compensation meansModern: deterministic phase-correction interval
3Recirculating Digital Color Register
Two four-bit shift registers accept color bits from RAM and repeatedly circulate them at the master-clock rate.

Registers 36 and 37 receive eight bits in parallel at 1 MHz. In color mode they recirculate the data at 14.31818 MHz; phase-select multiplexer 38 chooses staged output bits so the television receives an appropriate color-phase signal without a separate analog color generator.

19th-C. Term: recirculating shift registerModern: clocked digital serializer with feedback
Engineering Principles & Equations

Governing Equations & Engineering Principles

Authored explanation paired with its stated mathematical relation

Two-Phase Non-Conflicting Time-Multiplexed DRAM Arbitration

Computer Architecture & Digital LogicClaim 1
Mathematical Governing Law
Terms:
Plain English DecoderHover or tap any highlighted phrase
The equals half the period of the minus , interleaved seamlessly so the while the .
taccesst_{\text{access}}
Memory Access Window
Time duration allocated per cycle for DRAM read/write (approx 488 nanoseconds)
Nanoseconds (ns)

Because dynamic RAM access completes in under 400 ns, both the CPU and the video display hardware can complete a full read cycle within a single 978 ns clock period.

Physical Principle & Engineering Insight

Prior microcomputers like the Altair or TRS-80 required separate, expensive dual-ported RAM or caused annoying screen flicker when the CPU accessed video memory. Wozniak realized that 6502 CPUs only use the bus during phase 2 of the clock, using simple TTL multiplexers to interleave video fetches into phase 1 with zero extra parts.

Historical Context: US 4136359 made the Apple II the first practical, affordable personal computer with full color graphics, launching the PC revolution.

Shift-Register Dot Phase Delay & NTSC Color Artifacting

Video Processing & Digital LogicClaim 1
Mathematical Governing Law
Terms:
Plain English DecoderHover or tap any highlighted phrase
The synthesized is created by locking to the while delaying pixels by in from the , generating green, violet, blue, and orange without expensive color encoder chips.
Δϕcolor\Delta \phi_{\text{color}}
NTSC Color Phase Shift
Phase angle relative to the standard 3.579545 MHz3.579545\text{ MHz} color burst reference (0∘,90∘,180∘,270∘0^\circ, 90^\circ, 180^\circ, 270^\circ)
Degrees / Radians

Standard NTSC televisions decode phase angle as hue: 0∘0^\circ produces green, 90∘90^\circ produces violet/magenta, 180∘180^\circ produces orange, and 270∘270^\circ produces blue.

Physical Principle & Engineering Insight

Wozniak synthesized composite color video using digital shift registers and clock division, producing crisp 4-color high-resolution graphics with only $15 worth of standard 7400-series TTL chips instead of expensive analog encoders.

Historical Context: US 4136359 enabled the Apple II to output high-resolution color graphics directly to standard home color televisions, launching the personal computer revolution.

Composite NTSC Video Scanline Timing & Sync Circuitry

Display Synchronization & Digital ArchitectureClaim 2
Mathematical Governing Law
Terms:
Plain English DecoderHover or tap any highlighted phrase
Total is generated by counting exactly of derived from , yielding the standard and .
TscanlineT_{\text{scanline}}
Horizontal Scanline Period
Time duration to scan one complete horizontal line of 280 pixels plus blanking (63.555 μs63.555\,\mu\text{s})
Microseconds (\mu s)

Matches standard NTSC broadcast line duration within 0.05%, allowing standard consumer color television sets to lock sync without jitter.

Physical Principle & Engineering Insight

By aligning 65 CPU clock cycles to exactly one NTSC scanline interval (63.555 μs), Wozniak eliminated memory arbitration wait-states, letting the CPU and video display share RAM simultaneously without flicker.

Historical Context: This zero-wait-state shared DRAM architecture made the Apple II the fastest and most cost-effective microcomputer of its generation.

Line-to-line chroma phase correctionAuthored Principle 1
Stated relation

Each 15,734 Hz line contains three and one-half 3.579545 MHz chroma cycles; a two-cycle delay at 14.31818 MHz supplies one-half chroma cycle.

An odd half-cycle remainder reverses the chroma phase on the next line. The disclosed delay adds exactly that missing half-cycle before normal counting resumes, so a vertical color edge does not alternate phase on adjacent raster lines.
Digital color generation by recirculationAuthored Principle 2
Stated relation

Eight RAM bits load two four-bit registers at 1 MHz and are recirculated at 14.31818 MHz.

The source's engineering move is temporal: it converts stored bit patterns into the required frequency components by clocking and phase-selecting them, rather than producing independent continuous-wave color signals and mixing them.

Interactive Schematic Sheet (Fig. 1)

CPU 10, ROM 14, RAM 23, video generator 25, address multiplexer 28, and timing and synchronization generator 15 as printed in the source.

1.00x
US 4,136,359 · FIG. 1MOS 6502MUX48KB RAMVideo Gen
Tap any numbered pin3 Curated Callouts
Callout Pin Inspector

Select Any Numbered Pin

Click pins on the schematic or select from the list below to inspect historical specifications.

Why It Still Matters

The patent is a clear period example of treating a television display as a timing problem as much as a memory problem. Its complete source reading preserves the counter sequence, frequencies, color codes, and figures that explain why a small delay could make digital color graphics legible on a standard raster display.

Legal Claims Decoder (8 Numbered Claims)

Compare dense legalistic claims directly with decoded plain-English functional specifications.
Claim #1Independent Master Claim
1/8
Verbatim Historical Legal Text
“In a microcomputer for use with a video display an improved timing apparatus comprising: a timing reference means for providing a color reference signal for said video display; a horizontal synchronization means for providing horizontal synchronization signals for said display, said synchronization means coupled to said timing reference means for synchronization with said reference means such that said synchronization signals occur at an odd-submultiple of said color reference signal; timing compensation means coupled to said timing reference means and said horizontal synchronization means for adjusting said horizontal synchronization signals such that said horizontal synchronization signals are in phase relationship with said color reference signal; whereby the color graphics on a raster scanned cathode ray tube are sharply defined in the vertical direction.”
Plain English Engineering Translation
Claims a video-display timing apparatus with three linked pieces: a color-reference source, horizontal synchronization that occurs at an odd submultiple of that reference, and a compensation circuit that adjusts horizontal timing so the signals remain phase-related. The claimed result is vertically sharp color graphics on a raster CRT.
Key Protected Innovations:
color referenceodd-submultiple horizontal synctiming compensation

The Historical Bottleneck

The grant identifies a compatibility problem between digital microcomputer information and ordinary raster-scanned television receivers: maintaining near-standard horizontal synchronization while keeping vertical color lines coherent.

Why Prior Art Failed

  • •An odd-submultiple horizontal timing relationship produces a line-to-line chroma phase reversal and ragged vertical color lines unless corrected.
  • •An even-submultiple workaround moves horizontal synchronization away from its standard frequency and can require receiver adjustment.
  • •Earlier color generation stored four digital bits but used separate pure-color generation, gating, and mixing circuitry that the source calls complex.
The Breakthrough Insight
“Treat the chroma phase reversal as a deterministic counter-sequence error: extend the sequence by two master-clock cycles at the prescribed event, then use recirculating digital shift registers to turn RAM color bits into the display signal.”

Patent Wars & Legal Litigations

Vs. Franklin Computer Corporation (ACE 1000 Litigation)Infringement Challenge
Rival Claim & Defense:
Franklin Computer manufactured the Franklin ACE 1000 Apple II clone, arguing that video timing, ROM firmware, and system display controllers were utilitarian mechanical schemes ineligible for proprietary legal protection.
Litigation Conflict:
Apple sued Franklin in 1982 in federal court (Apple Computer, Inc. v. Franklin Computer Corp.), asserting US Patent 4,136,359 and software copyright over Apple II display generation and ROM routines.
Final Resolution & Judicial Outcome:
The Third Circuit Court of Appeals ruled in Apple's favor, establishing the foundational legal precedent that microcode, firmware, and video timing controllers embedded in silicon are protectable intellectual property.
After the Grant
This record is limited to what the reviewed 1979 grant establishes. The complete manual source edition preserves the circuit, timing values, color table, and all eight printed claims; later product history and other Apple II architecture claims require separate evidence.
Civilizational Impact
The source captures a concrete engineering route from low-cost digital logic to a usable color raster display: tie color, horizontal sync, and digital data circulation to one clock, then explicitly correct the timing mismatch that makes vertical color edges unstable.
Technological Lineage & Descent

The Silicon Microelectronics Revolution

From Punched-Card Tabulators to Multi-Touch Human Interfaces

The digital computation lineage that replaced mechanical gear teeth with point-contact semiconductor switches, monolithic planar circuits, personal computers, and touch glass.

1889Electromechanical Data Storage
US 395,781

Record-Card Statistical Compiler

Conductive mercury cup contacts sensing punched holes in structured card records.

1950Solid-State Transistor Origin
US 2,524,035

Bardeen and Brattain Point-Contact Transistor

Point-contact emitter/collector gold cat-whiskers modulating minority carrier diffusion.

1961Planar Monolithic Circuit
US 2,981,877

Oxide-insulated semiconductor leads

Oxide passivation, photolithographic isolation, and evaporated aluminium leads on silicon.

1964Miniaturized Solid Circuit
US 3,138,743

Jack Kilby Monolithic Integrated Circuit

Semiconductor wafer containing active transistors and passive resistive components.

1970Interactive Spatial Input
US 3,541,541

Two-Wheel Position Indicator

Orthogonal rolling wheels driving potentiometers to translate hand motion to screen cursor.

1979Integrated MicrocomputerThis Patent
US 4,136,359

Wozniak Video Timing and Color Circuit

Shared-RAM timing generator enabling flicker-free color microprocessor video generation.

2001Global Information Graph
US 6,285,999

Google PageRank Algorithm

Eigenvector centrality algorithm weighting web document importance by hyperlink graph.

2009Capacitive Gestural Surface
US 7,479,949

Apple iPhone Multi-Touch Heuristics

Mutual capacitance sensor matrix resolving concurrent discrete finger touch trajectories.