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Archaic Legal Glossary & Citations

“Letters Patent”14th–20th Century
19th-C Meaning:

Open public letters from a monarch or government (literae patentes) granting monopoly rights.

Modern Engineering Decoded:Issued USPTO utility or design patent publication.
Historical note: Contrasted with 'letters close' (private sealed royal correspondence).
“In testimony whereof”19th Century
19th-C Meaning:

Formal concluding legal formula affirming under oath the execution of the instrument.

Modern Engineering Decoded:Inventor and witness digital/physical signatures.
Historical note: Required two witness attestations in 19th-century USPTO filing procedure.
“Aeroplane”Early 20th Century (Wright era)
19th-C Meaning:

A flat or cambered lifting aerofoil surface supported dynamically by air pressure.

Modern Engineering Decoded:Wing / Airfoil lifting surface (later evolved to mean the entire motorized aircraft).
Historical note: The Wrights used 'aeroplane' to denote the individual fabric-covered wings.
“Undulating Current”19th Century (Bell era)
19th-C Meaning:

An electric current whose magnitude varies continuously and periodically without interruption.

Modern Engineering Decoded:Continuous analog AC or audio-frequency electrical waveform.
Historical note: Bell's central legal weapon against telegraph companies who relied on pulsed DC make-and-break circuits.
“Subdivision of the Electric Light”1870s–1880s (Edison era)
19th-C Meaning:

The problem of operating numerous small domestic lamps off a single electrical generator.

Modern Engineering Decoded:Parallel circuit wiring of high-resistance incandescent electrical loads.
Historical note: Pundits claimed it was physically impossible until Edison increased filament resistance to 100 ohms.
“Optically Anisotropic Solution”1960s (Kwolek era)
19th-C Meaning:

A liquid solution that exhibits direction-dependent refractive indices due to molecular alignment.

Modern Engineering Decoded:Liquid crystalline nematic phase polymer dope.
Historical note: Technicians initially tried to throw out Kwolek's cloudy solution thinking it was contaminated.
“Unitary Body of Semiconductor Material”1950s–1960s (Noyce era)
19th-C Meaning:

A single continuous crystal structure of silicon or germanium.

Modern Engineering Decoded:Monolithic single-crystal silicon die / integrated circuit wafer.
Historical note: Differentiated Noyce's monolithic planar circuit from Jack Kilby's hybrid flying-wire prototype.
“Peculiar and Novel Construction”19th Century
19th-C Meaning:

A distinctive, patentable structural arrangement not found in prior art.

Modern Engineering Decoded:Novel and non-obvious mechanical embodiment under 35 U.S.C. § 103.
Historical note: Standard 19th-century legal terminology establishing novelty.

Museum Broadside & Archival Print Edition

Authentic archival layout formatted for framing, study, and high-resolution printing

Paper:
Theme:
The United States Patent & Trademark Archive

Historical Specification & Engineering Broadside

Curated, Verified & Restored by Classic Patents (classic-patents.com)
INFORMATION STORAGE DEVICESSequential Charge Packet Storage and Transfer Through Induced Semiconductor Potential Wells
US 3,858,232Class: 357/24
Inventor(s):Willard S. Boyle, George E. Smith
Origin / Location:Murray Hill, New Jersey
Grant & Filing:Filed November 9, 1971 · Granted December 31, 1974

I. Historical Context & Grant Summary

United States Patent 3,858,232 discloses the Charge-Coupled Device (CCD), invented at Bell Telephone Laboratories by Willard S. Boyle and George E. Smith. The device stores and manipulates information in the form of discrete packets of minority charge carriers (photoelectrons) confined within mobile electrostatic potential energy wells created by an array of closely spaced MOS gate electrodes on a single-conductivity semiconductor substrate. By sequentially clocking adjacent electrode voltages, potential wells are deepened and collapsed in an overlapping sequence, smoothly transferring charge packets along a continuous channel with over 99.999% transfer efficiency. The CCD replaced bulky electron-beam vacuum tubes (vidicons) and magnetic storage with solid-state digital imaging, winning Boyle and Smith the 2009 Nobel Prize in Physics.

II. Core Mechanism & Scientific Principles

In October 1969 at Bell Telephone Laboratories, physicists Willard Boyle and George Smith were asked to create a solid-state memory technology to compete with magnetic bubble memory. In just one hour of brainstorming at a blackboard, they conceived the Charge-Coupled Device (CCD). Instead of building complex circuits with millions of separate transistors and wires, they realized that electric voltages applied to surface metal plates could create invisible 'buckets' (potential energy wells) in a flat silicon crystal. Stored electrical charges (representing digital 1s/0s or analog pixel brightness) could be poured like water from bucket to bucket simply by clocking the voltages. When exposed to light, silicon naturally converts photons into electron packets, turning the CCD into an electronic eye that revolutionized astronomy, digital cameras, and medical imaging.

Physical Operation:A CCD operates through a 3-step sequence: (1) Charge Generation & Integration: Incident light generates electron-hole pairs in p-type silicon via the photoelectric effect. A positive gate voltage ($V_G \approx 10\text{ V}$) repels majority positive holes, creating a deep depletion potential well ($\psi_s \approx 8\text{ V}$) that captures photoelectrons. (2) Three-Phase Clocked Transfer: Three adjacent gate electrodes ($\Phi_1, \Phi_2, \Phi_3$) are clocked in overlapping phase cycles. When $\Phi_2$ is energized while $\Phi_1$ is still high, an overlapping potential well opens, and thermal diffusion plus fringing electric fields drive electrons into the new well. When $\Phi_1$ is ramped down, the electrons are trapped under $\Phi_2$. Repeating this across thousands of gates transfers charge with over 99.999% efficiency (CTE). (3) Output Readout: At the channel end, charge packets are dumped onto a floating diffusion sensing node connected to an on-chip source-follower MOSFET, converting charge packets ($Q$) into low-noise analog output voltage ($V_{\text{out}} = Q / C_{\text{FD}}$).
Governing Formulation:
MOS Deep Depletion Surface Potential:\psi_s = V_G - V_{\text{FB}} + V_0 - \sqrt{2 (V_G - V_{\text{FB}}) V_0 + V_0^2} \quad \text{where} \quad V_0 = \frac{q \epsilon_{\text{Si}} N_A}{C_{\text{ox}}^2}
Charge Transfer Efficiency & Diffusion Kinetics:\text{CTE} = 1 - \text{CTI} = 1 - \left[ \exp\left(-\frac{\pi^2 D_n t_{\text{transfer}}}{4 L_{\text{gate}}^2}\right) + \epsilon_{\text{trap}} \right]
Photoelectric Carrier Generation & Integration:N_e = \min\left(Q_{\text{max}}, \eta_{\text{QE}} \frac{P_{\text{opt}} A_{\text{pixel}} t_{\text{int}}}{h \nu} + N_{\text{dark}}\right)

III. The Granted Legal Monopoly (Key Claims)

Claim 1 (Independent)Continuous single-conductivity charge-transfer channel

Master apparatus claim for a charge transfer device wherein information-bearing charge carriers are stored in and serially transferred through a plurality of induced potential energy wells along a continuous semiconductor medium that is characterized by having a uniform single conductivity type without intermediate p-n junctions.

Claim 2 (Independent)Single-conductivity semiconductor underlying transfer electrodes

Protects a charge transfer apparatus wherein discrete minority charge carrier packets are stored and serially translated along a semiconductor medium by sequentially applying voltages through field electrodes, characterized in that the semiconductor region directly underlying each transfer electrode is of a single conductivity type.

Claim 3 (Dependent)Metal-Insulator-Semiconductor (MIS) gate stack architecture

Covers the charge transfer apparatus of claim 2 wherein the single-conductivity semiconductor storage medium is covered by an insulating dielectric layer, with the plurality of field electrodes disposed directly on top of the insulating layer.

IV. Mechanical Organ Breakdown

MOS Depletion Potential Well ArrayTerm: “potential energy minima in semiconductor” → MOS potential well / CCD pixel photogate

Array of metal-oxide-semiconductor gate electrodes overlying p-type silicon substrate.

3-Phase Polysilicon Clocked Shift RegisterTerm: “sequential field-electrode translating means” → multi-phase CCD charge shift register

Sequential tri-level gate electrodes driven by overlapping clock waveforms.

Single-Conductivity Channel ArchitectureTerm: “channel of single conductivity type” → charge-coupled transport channel

Continuous semiconductor channel formed without intermediate p-n junction diffusions.

Floating Diffusion Readout NodeTerm: “charge detecting device” → floating diffusion amplifier node

Low-capacitance output sensing diode with reset MOSFET and source-follower buffer.

CLASSIC PATENTS DIGITAL ARCHIVE • PERMANENT EXHIBIT ID: us-3858232-boyle-smith-ccd
classic-patents.com/patents/us-3858232-boyle-smith-ccd
Original USPTO PDF
Classic Patents/US 3,858,232
Information Age (1960–1990)Digital Imaging & Optoelectronics

Boyle & Smith Charge-Coupled Device (CCD)

US 3,858,232

Sequential Charge Packet Storage and Transfer Through Induced Semiconductor Potential Wells

Inventor(s)Willard S. Boyle, George E. Smith
Grant DateDecember 31, 1974
Filing DateNovember 9, 1971
LocationMurray Hill, New Jersey
United States Patent 3,858,232 discloses the Charge-Coupled Device (CCD), invented at Bell Telephone Laboratories by Willard S. Boyle and George E. Smith. The device stores and manipulates information in the form of discrete packets of minority charge carriers (photoelectrons) confined within mobile electrostatic potential energy wells created by an array of closely spaced MOS gate electrodes on a single-conductivity semiconductor substrate. By sequentially clocking adjacent electrode voltages, potential wells are deepened and collapsed in an overlapping sequence, smoothly transferring charge packets along a continuous channel with over 99.999% transfer efficiency. The CCD replaced bulky electron-beam vacuum tubes (vidicons) and magnetic storage with solid-state digital imaging, winning Boyle and Smith the 2009 Nobel Prize in Physics.
USPTO PDF
Audio Engineering Breakdown~2 min listen

Listen to the narrated mechanical breakdown and civilizational context

Engineering Analysis & Physical Principles

How It Works: Step-by-Step Mechanical & Physical Breakdown

In October 1969 at Bell Telephone Laboratories, physicists Willard Boyle and George Smith were asked to create a solid-state memory technology to compete with magnetic bubble memory. In just one hour of brainstorming at a blackboard, they conceived the Charge-Coupled Device (CCD). Instead of building complex circuits with millions of separate transistors and wires, they realized that electric voltages applied to surface metal plates could create invisible 'buckets' (potential energy wells) in a flat silicon crystal. Stored electrical charges (representing digital 1s/0s or analog pixel brightness) could be poured like water from bucket to bucket simply by clocking the voltages. When exposed to light, silicon naturally converts photons into electron packets, turning the CCD into an electronic eye that revolutionized astronomy, digital cameras, and medical imaging.
The Core Breakthrough Mechanism

A CCD operates through a 3-step sequence: (1) Charge Generation & Integration: Incident light generates electron-hole pairs in p-type silicon via the photoelectric effect. A positive gate voltage (VG≈10 VV_G \approx 10\text{ V}) repels majority positive holes, creating a deep depletion potential well (ψs≈8 V\psi_s \approx 8\text{ V}) that captures photoelectrons. (2) Three-Phase Clocked Transfer: Three adjacent gate electrodes (Φ1,Φ2,Φ3\Phi_1, \Phi_2, \Phi_3) are clocked in overlapping phase cycles. When Φ2\Phi_2 is energized while Φ1\Phi_1 is still high, an overlapping potential well opens, and thermal diffusion plus fringing electric fields drive electrons into the new well. When Φ1\Phi_1 is ramped down, the electrons are trapped under Φ2\Phi_2. Repeating this across thousands of gates transfers charge with over 99.999% efficiency (CTE). (3) Output Readout: At the channel end, charge packets are dumped onto a floating diffusion sensing node connected to an on-chip source-follower MOSFET, converting charge packets (QQ) into low-noise analog output voltage (Vout=Q/CFDV_{\text{out}} = Q / C_{\text{FD}}).

Interactive Real-Time Physical Simulation

Drag to rotate · Pinch to zoom · Shared controls update the displayed model
INITIALIZING THREE.JS WEBGL SIMULATION...
Figure 2 Single-Conductivity Charge-Transfer Topology.
Host-Model Telemetry/Computed Readout
Figure 2 Single-Conductivity Charge-Transfer Topology
Figure 3 Active Phase
Reader Scenario
Phi 1of 3[1]
Printed Input Pattern
Source
1101Figure 3[1]
Pulse-Overlap Relation
Reader Scenario
0.50 (SATISFIED)t_p / delta-t > 1/3[1]
Claim 1 Storage Medium
Source
CONTINUOUSsingle conductivity type[1]
Quantitative CTE / Charge / Power
Source Refusal
REFUSEDmissing operating inputs[1]
Pulse Width / Initiation Interval0.5 t_p / delta-t
Visible Phase-Step Rate1.2 Hz display
Relative Potential-Well Depth0.78 normalized
Clock Sequence Running1 boolean
Interval ghosts
Pulse overlap0.5 t_p / delta-t · [0.3333333333333333, 0.8]
Fidelity / MMS residual
Figure 3 pulse-overlap inequality
model0.500 t_p / delta-t
reference> 0.333 t_p / delta-t
residual+0.167 t_p / delta-t
Dated scenarios

Detailed Component Architecture

1MOS Depletion Potential Well Array
Array of metal-oxide-semiconductor gate electrodes overlying p-type silicon substrate.

Positive gate bias (VG=5 to 15 VV_G = 5\text{ to }15\text{ V}) creates surface depletion layers (ψs≈VG−VFB+V0−2(VG−VFB)V0+V02\psi_s \approx V_G - V_{\text{FB}} + V_0 - \sqrt{2(V_G - V_{\text{FB}})V_0 + V_0^2}), forming potential energy minima with full-well storage capacity up to 3×1053 \times 10^5 electrons per 100 μm2100\ \mu\text{m}^2 pixel.

19th-C. Term: potential energy minima in semiconductorModern: MOS potential well / CCD pixel photogate
23-Phase Polysilicon Clocked Shift Register
Sequential tri-level gate electrodes driven by overlapping clock waveforms.

Three-phase clocking (Φ1,Φ2,Φ3\Phi_1, \Phi_2, \Phi_3) produces directional traveling potential wells with transit times under 50 nanoseconds, achieving Charge Transfer Inefficiency below 10−510^{-5} (CTE>0.99999\text{CTE} > 0.99999).

19th-C. Term: sequential field-electrode translating meansModern: multi-phase CCD charge shift register
3Single-Conductivity Channel Architecture
Continuous semiconductor channel formed without intermediate p-n junction diffusions.

Eliminates p-n junctions between adjacent bits, dramatically reducing parasitic capacitance, dark current leakage, and silicon surface area requirements.

19th-C. Term: channel of single conductivity typeModern: charge-coupled transport channel
4Floating Diffusion Readout Node
Low-capacitance output sensing diode with reset MOSFET and source-follower buffer.

Converts discrete electron packets into microvolt-level analog signals with extremely low read noise (σread<5 e−\sigma_{\text{read}} < 5\text{ e}^- rms) and dynamic range exceeding 80 dB.

19th-C. Term: charge detecting deviceModern: floating diffusion amplifier node
Engineering Principles & Equations

Governing Equations & Engineering Principles

Authored explanation paired with its stated mathematical relation

Claim 2: Sequential Transfer Between Storage Minima

Source-Bound Semiconductor Information StorageClaim 2
Mathematical Governing Law
Terms:
Plain English DecoderHover or tap any highlighted phrase
Claim 2 treats as stored information. A sequential electrode field establishes a so the stored charge can transfer before the earlier minimum is removed.
minoritycarriersminority carriers
Stored minority charge carriers
The minority carriers identified by the source as the information-bearing charge stored in a semiconductor medium.
Claim 2 information-bearing element

The source describes charge storage and transfer in a semiconductor medium. It does not supply a full-well capacity, quantum efficiency, sensor-noise value, or image-resolution measurement.

Physical Principle & Engineering Insight

This card is limited to the Claim 2 storage-and-transfer relation. The complete original-text face remains readable while the manual literal ledger and non-lossy companions are completed, so the site does not present a quantitative CCD, camera, or later-product model for US 3,858,232.

Historical Context: The card identifies the source's stated information-storage move without recasting this grant as the separate later CCD patent formerly attached to the route.

MOS Deep Depletion Surface PotentialAuthored Principle 1
Stated relationψs=VG−VFB+V0−2(VG−VFB)V0+V02whereV0=qϵSiNACox2\psi_s = V_G - V_{\text{FB}} + V_0 - \sqrt{2 (V_G - V_{\text{FB}}) V_0 + V_0^2} \quad \text{where} \quad V_0 = \frac{q \epsilon_{\text{Si}} N_A}{C_{\text{ox}}^2}
Positive gate voltage repels mobile holes from the surface, creating an unshielded negative acceptor space-charge depletion region with a deep electrostatic potential well.
Charge Transfer Efficiency & Diffusion KineticsAuthored Principle 2
Stated relationCTE=1−CTI=1−[exp⁡(−π2Dnttransfer4Lgate2)+ϵtrap]\text{CTE} = 1 - \text{CTI} = 1 - \left[ \exp\left(-\frac{\pi^2 D_n t_{\text{transfer}}}{4 L_{\text{gate}}^2}\right) + \epsilon_{\text{trap}} \right]
Thermal diffusion and self-induced electrostatic drift govern the rapid transit of electrons between adjacent potential wells during clock phase overlap.
Photoelectric Carrier Generation & IntegrationAuthored Principle 3
Stated relationNe=min⁡(Qmax,ηQEPoptApixeltinthν+Ndark)N_e = \min\left(Q_{\text{max}}, \eta_{\text{QE}} \frac{P_{\text{opt}} A_{\text{pixel}} t_{\text{int}}}{h \nu} + N_{\text{dark}}\right)
Incident photons with energy exceeding the 1.12 eV silicon bandgap create electron-hole pairs collected and stored linearly during the optical integration frame time.

Interactive Schematic Sheet (Figure 1a)

Schematic cross section of a three-phase charge-coupled device shift register showing the silicon substrate 11, insulating oxide layer 12, and sequentially clocked gate electrodes 13.

1.00x
US 3,858,232 · FIGURE 1Aφ1 · φ2 · φ3 charge packets
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Why It Still Matters

The CCD revolutionized human vision and scientific discovery. It enabled digital photography, smartphone cameras, camcorders, medical endoscopy, barcode scanners, and astronomical imaging—including the Hubble Space Telescope and deep-space planetary probes—earning Boyle and Smith the 2009 Nobel Prize in Physics.

Legal Claims Decoder (32 Numbered Claims)

Compare dense legalistic claims directly with decoded plain-English functional specifications.
Claim #1Independent Master Claim
1/32
Verbatim Historical Legal Text
“In a charge transfer apparatus of the type for storage and serial transfer of charge carriers localized in a plurality of induced potential energy minima along a portion of a semiconductor charge storage medium by sequentially applying different potentials to successive portions of the surface of the medium through a plurality of electrodes, the invention characterized in that the charge storage medium is of a single conductivity type.”
Plain English Engineering Translation
Master apparatus claim for a charge transfer device wherein information-bearing charge carriers are stored in and serially transferred through a plurality of induced potential energy wells along a continuous semiconductor medium that is characterized by having a uniform single conductivity type without intermediate p-n junctions.
Key Protected Innovations:
Continuous single-conductivity charge-transfer channelInduced electrostatic potential energy wellsSequential field-electrode clocking
Historical Legal Impact:
The foundational master patent claim for Charge-Coupled Devices, establishing broad legal protection for potential-well charge packet storage and transfer.

The Historical Bottleneck

In the late 1960s, electronic imaging required fragile, bulky, high-voltage vacuum tubes (Vidicons and Image Orthicons) with raster electron beams, while computer memory relied on complex magnetic cores or emerging transistor circuits that required separate wiring for every bit.

Why Prior Art Failed

  • •Vidicon camera tubes required high vacuum, high voltages (>1000V), and had severe image lag and burn-in
  • •Semiconductor shift registers required separate isolated p-n junction diffusions for every bit
  • •Magnetic core memory was expensive, bulky, and power-hungry
The Breakthrough Insight
“Boyle and Smith realized that mobile electric charge packets could be stored in surface potential wells and shifted continuously through a single homogeneous semiconductor substrate simply by manipulating the voltages on a sequence of surface metal plates.”

Patent Wars & Legal Litigations

Vs. Texas Instruments & Fairchild SemiconductorInfringement Challenge
Rival Claim & Defense:
Bucket-Brigade Devices (BBD) and Charge-Injection Devices (CID)
Litigation Conflict:
Philips had developed the Bucket-Brigade Device (BBD) using discrete transistors and capacitors. Bell Labs established that the CCD's continuous single-conductivity substrate without intermediate p-n diffusions was fundamentally superior in packing density, speed, and transfer efficiency.
Final Resolution & Judicial Outcome:
Boyle and Smith's patent US 3,858,232 was granted on December 31, 1974, establishing Bell Labs' foundational priority for charge-coupled devices.
Civilizational Impact
The CCD democratized digital visual culture, eliminated photographic film development, made modern medical endoscopy non-invasive, and allowed astronomers to peer back to the dawn of the universe with quantum efficiency exceeding 90%.
Historical Fact
Willard Boyle and George Smith conceived the entire architecture of the Charge-Coupled Device in approximately one hour of intense brainstorming on an afternoon in October 1969.